The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a stricture for reducing lateral fringe capacitance in semiconductor devices and a method of forming the same.
The continuing trend in the semiconductor industry of forming more and more circuit devices into a given area has resulted in significant improvements in both the performance of individual integrated circuits and of electronic devices that employ integrated circuits. In a typical integrated circuit, individual circuit elements or groups of elements are generally electrically connected to one another by a metallization process, in which layers of metal are deposited and patterned to form metal lines which complete the circuit as designed. Individual metal lines formed within patterned metal layers are insulated from one another by layers referred to as interlevel dielectrics. These interlevel dielectrics insulate the metal lines from any undesired electrical contact with other metal lines (whether located in the same or another metal layer, and with other circuit elements.
A typical dual-damascene structure is fabricated by depositing a dielectric material, defining the lines and vias through lithography and etching, then metallizing to fill the patterned lines and vias, the polishing the excess metal to completed lines. After chemical mechanical polishing (CMP), the surface is nearly flat and the current carrying lines are isolated from adjacent lines to complete the circuitry. At this point, the copper metal layer is typically capped and a subsequent dielectric layer is deposited.
However, one undesirable side effect of the increasing density of integrated circuits described above is a parasitic lateral capacitance between adjacent metal lines in a given metal layer. This unneeded capacitance slows circuit performance by causing too much buildup of charge where none is needed, thereby slowing the buildup of charge at circuit elements where it is needed.
FIG. 1 illustrates a cross sectional view of partially formed, conventional integrated circuit device 100. An interlevel dielectric (ILD) layer 102, such as silicon dioxide (SiO2) for example, has a plurality of conductive metal lines 104 formed therein. After a planarizing step used to polish the metal fill material 104 down to the top of the ILD layer 102, a dielectric cap layer 106 such as NBLoK (nitrogen-doped silicon carbide) is formed thereupon. Whereas the dielectric constant of the ILD layer 102 is on the order of about 2.5-3.0, the dielectric constant of the NBLoK cap layer 106 is about 6.0.
The lateral capacitance (C) between adjacent metal lines 104 of the structure 100 is influenced by several factors, two of which are: (1) the capacitance due to the ILD material 102 between the lines 102 and (2) the fringe capacitance as a result of the overlaying NBLoK cap 106. Although the capacitance contribution due to the ILD material 102 can be lowered by replacing silicon dioxide with a lower-k dielectric, it is much tougher to simply replace the NBLoK cap layer, as such a layer serves multiple functions that make it tough to replace as a material.
Accordingly, it would be desirable to be able to reduce the fringe contribution of lateral capacitance in metal lines in a manner that retains the benefits of using a higher dielectric constant capping layer.